//##==============================================================================
//##=== This script is generate by genswconfig.pl from .\00_cv181x_Pinlist_20210827.xls
//##=== Generate Time stamp is : 2021-08-27 20:43:11
//##==============================================================================

#ifndef __CV181X_PINLIST_SWCONFIG_H__
#define __CV181X_PINLIST_SWCONFIG_H__

#define CAM_MCLK0__CAM_MCLK0 0
#define CAM_MCLK0__AUX1 2
#define CAM_MCLK0__XGPIOA_0 3
#define CAM_PD0__IIS1_MCLK 1
#define CAM_PD0__XGPIOA_1 3
#define CAM_PD0__CAM_HS0 4
#define CAM_RST0__XGPIOA_2 3
#define CAM_RST0__CAM_VS0 4
#define CAM_RST0__IIC4_SCL 6
#define CAM_MCLK1__CAM_MCLK1 0
#define CAM_MCLK1__AUX2 2
#define CAM_MCLK1__XGPIOA_3 3
#define CAM_MCLK1__CAM_HS0 4
#define CAM_PD1__IIS1_MCLK 1
#define CAM_PD1__XGPIOA_4 3
#define CAM_PD1__CAM_VS0 4
#define CAM_PD1__IIC4_SDA 6
#define IIC3_SCL__IIC3_SCL 0
#define IIC3_SCL__XGPIOA_5 3
#define IIC3_SDA__IIC3_SDA 0
#define IIC3_SDA__XGPIOA_6 3
#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__DBG_7 7
#define EMMC_RSTN__EMMC_RSTN 0
#define EMMC_RSTN__XGPIOA_21 3
#define EMMC_RSTN__AUX2 4
#define EMMC_DAT2__EMMC_DAT_2 0
#define EMMC_DAT2__SPINOR_HOLD_X 1
#define EMMC_DAT2__SPINAND_HOLD 2
#define EMMC_DAT2__XGPIOA_26 3
#define EMMC_CLK__EMMC_CLK 0
#define EMMC_CLK__SPINOR_SCK 1
#define EMMC_CLK__SPINAND_CLK 2
#define EMMC_CLK__XGPIOA_22 3
#define EMMC_DAT0__EMMC_DAT_0 0
#define EMMC_DAT0__SPINOR_MOSI 1
#define EMMC_DAT0__SPINAND_MOSI 2
#define EMMC_DAT0__XGPIOA_25 3
#define EMMC_DAT3__EMMC_DAT_3 0
#define EMMC_DAT3__SPINOR_WP_X 1
#define EMMC_DAT3__SPINAND_WP 2
#define EMMC_DAT3__XGPIOA_27 3
#define EMMC_CMD__EMMC_CMD 0
#define EMMC_CMD__SPINOR_MISO 1
#define EMMC_CMD__SPINAND_MISO 2
#define EMMC_CMD__XGPIOA_23 3
#define EMMC_DAT1__EMMC_DAT_1 0
#define EMMC_DAT1__SPINOR_CS_X 1
#define EMMC_DAT1__SPINAND_CS 2
#define EMMC_DAT1__XGPIOA_24 3
#define JTAG_CPU_TMS__CV_2WTMS_CR_4WTMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TMS__VO_D_28 7
#define JTAG_CPU_TCK__CV_2WTCK_CR_4WTCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define JTAG_CPU_TCK__VO_D_29 7
#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
#define JTAG_CPU_TRST__XGPIOA_20 3
#define JTAG_CPU_TRST__VO_D_30 6
#define IIC0_SCL__CV_SCL0__CR_4WTDI 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__CV_SDA0__CR_4WTDO 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__VO_D_31 5
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PWR_SEQ3__PWR_SEQ3 0
#define PWR_SEQ3__PWR_GPIO_5 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_IR0 1
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_WAKEUP1__PWR_WAKEUP1 0
#define PWR_WAKEUP1__PWR_IR1 1
#define PWR_WAKEUP1__PWR_GPIO_7 3
#define PWR_WAKEUP1__UART1_TX 4
#define PWR_WAKEUP1__IIC4_SCL 5
#define PWR_WAKEUP1__EPHY_LNK_LED 6
#define PWR_WAKEUP1__WG0_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define PWR_ON__PWR_ON 0
#define PWR_ON__PWR_GPIO_9 3
#define PWR_ON__UART1_RX 4
#define PWR_ON__IIC4_SDA 5
#define PWR_ON__EPHY_SPD_LED 6
#define PWR_ON__WG0_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__CV_4WTMS_CR_SDA0 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__CV_4WTCK_CR_2WTCK 7
#define CLK32K__CLK32K 0
#define CLK32K__AUX0 1
#define CLK32K__CV_4WTDI_CR_SCL0 2
#define CLK32K__PWR_GPIO_10 3
#define CLK32K__PWM_2 4
#define CLK32K__KEY_COL0 5
#define CLK32K__CAM_MCLK0 6
#define CLK32K__DBG_0 7
#define CLK25M__CLK25M 0
#define CLK25M__AUX1 1
#define CLK25M__CV_4WTDO_CR_2WTMS 2
#define CLK25M__PWR_GPIO_11 3
#define CLK25M__PWM_3 4
#define CLK25M__KEY_COL1 5
#define CLK25M__CAM_MCLK1 6
#define CLK25M__DBG_1 7
#define IIC2_SCL__IIC2_SCL 0
#define IIC2_SCL__PWM_14 1
#define IIC2_SCL__PWR_GPIO_12 3
#define IIC2_SCL__UART2_RX 4
#define IIC2_SCL__KEY_COL2 7
#define IIC2_SDA__IIC2_SDA 0
#define IIC2_SDA__PWM_15 1
#define IIC2_SDA__PWR_GPIO_13 3
#define IIC2_SDA__UART2_TX 4
#define IIC2_SDA__IIS1_MCLK 5
#define IIC2_SDA__IIS2_MCLK 6
#define IIC2_SDA__KEY_COL3 7
#define UART2_TX__UART2_TX 0
#define UART2_TX__PWM_11 1
#define UART2_TX__PWR_UART1_TX 2
#define UART2_TX__PWR_GPIO_14 3
#define UART2_TX__KEY_ROW3 4
#define UART2_TX__UART4_TX 5
#define UART2_TX__IIS2_BCLK 6
#define UART2_TX__WG2_D0 7
#define UART2_RTS__UART2_RTS 0
#define UART2_RTS__PWM_8 1
#define UART2_RTS__PWR_GPIO_15 3
#define UART2_RTS__KEY_ROW0 4
#define UART2_RTS__UART4_RTS 5
#define UART2_RTS__IIS2_DO 6
#define UART2_RTS__WG1_D0 7
#define UART2_RX__UART2_RX 0
#define UART2_RX__PWM_10 1
#define UART2_RX__PWR_UART1_RX 2
#define UART2_RX__PWR_GPIO_16 3
#define UART2_RX__KEY_COL3 4
#define UART2_RX__UART4_RX 5
#define UART2_RX__IIS2_DI 6
#define UART2_RX__WG2_D1 7
#define UART2_CTS__UART2_CTS 0
#define UART2_CTS__PWM_9 1
#define UART2_CTS__PWR_GPIO_17 3
#define UART2_CTS__KEY_ROW1 4
#define UART2_CTS__UART4_CTS 5
#define UART2_CTS__IIS2_LRCK 6
#define UART2_CTS__WG1_D1 7
#define SD1_D3__PWR_SD1_D3_VO32 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2_VO33 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1_VO34 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0_VO35 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD_VO36 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__CAM_VS0 4
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK_VO37 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__CAM_HS0 4
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define RSTN__RSTN 0
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC3__CAM_MCLK0 1
#define ADC3__IIC4_SCL 2
#define ADC3__XGPIOB_1 3
#define ADC3__PWM_12 4
#define ADC3__EPHY_LNK_LED 5
#define ADC3__WG2_D0 6
#define ADC3__UART3_TX 7
#define ADC2__CAM_MCLK1 1
#define ADC2__IIC4_SDA 2
#define ADC2__XGPIOB_2 3
#define ADC2__PWM_13 4
#define ADC2__EPHY_SPD_LED 5
#define ADC2__WG2_D1 6
#define ADC2__UART3_RX 7
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define USB_ID__USB_ID 0
#define USB_ID__XGPIOB_4 3
#define USB_VBUS_EN__USB_VBUS_EN 0
#define USB_VBUS_EN__XGPIOB_5 3
#define PKG_TYPE0__PKG_TYPE0 0
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define MUX_SPI1_MISO__UART3_RTS 1
#define MUX_SPI1_MISO__IIC1_SDA 2
#define MUX_SPI1_MISO__XGPIOB_8 3
#define MUX_SPI1_MISO__PWM_9 4
#define MUX_SPI1_MISO__KEY_COL1 5
#define MUX_SPI1_MISO__SPI1_SDI 6
#define MUX_SPI1_MISO__DBG_14 7
#define MUX_SPI1_MOSI__UART3_RX 1
#define MUX_SPI1_MOSI__IIC1_SCL 2
#define MUX_SPI1_MOSI__XGPIOB_7 3
#define MUX_SPI1_MOSI__PWM_8 4
#define MUX_SPI1_MOSI__KEY_COL0 5
#define MUX_SPI1_MOSI__SPI1_SDO 6
#define MUX_SPI1_MOSI__DBG_13 7
#define MUX_SPI1_CS__UART3_CTS 1
#define MUX_SPI1_CS__CAM_MCLK0 2
#define MUX_SPI1_CS__XGPIOB_10 3
#define MUX_SPI1_CS__PWM_11 4
#define MUX_SPI1_CS__KEY_ROW3 5
#define MUX_SPI1_CS__SPI1_CS_X 6
#define MUX_SPI1_CS__DBG_16 7
#define MUX_SPI1_SCK__UART3_TX 1
#define MUX_SPI1_SCK__CAM_MCLK1 2
#define MUX_SPI1_SCK__XGPIOB_9 3
#define MUX_SPI1_SCK__PWM_10 4
#define MUX_SPI1_SCK__KEY_ROW2 5
#define MUX_SPI1_SCK__SPI1_SCK 6
#define MUX_SPI1_SCK__DBG_15 7
#define PAD_ETH_TXP__UART3_RX 1
#define PAD_ETH_TXP__IIC1_SCL 2
#define PAD_ETH_TXP__XGPIOB_25 3
#define PAD_ETH_TXP__PWM_13 4
#define PAD_ETH_TXP__CAM_MCLK0 5
#define PAD_ETH_TXP__SPI1_SDO 6
#define PAD_ETH_TXP__IIS2_LRCK 7
#define PAD_ETH_TXM__UART3_RTS 1
#define PAD_ETH_TXM__IIC1_SDA 2
#define PAD_ETH_TXM__XGPIOB_24 3
#define PAD_ETH_TXM__PWM_12 4
#define PAD_ETH_TXM__CAM_MCLK1 5
#define PAD_ETH_TXM__SPI1_SDI 6
#define PAD_ETH_TXM__IIS2_BCLK 7
#define PAD_ETH_RXP__UART3_TX 1
#define PAD_ETH_RXP__CAM_MCLK1 2
#define PAD_ETH_RXP__XGPIOB_27 3
#define PAD_ETH_RXP__PWM_15 4
#define PAD_ETH_RXP__CAM_HS0 5
#define PAD_ETH_RXP__SPI1_SCK 6
#define PAD_ETH_RXP__IIS2_DO 7
#define PAD_ETH_RXM__UART3_CTS 1
#define PAD_ETH_RXM__CAM_MCLK0 2
#define PAD_ETH_RXM__XGPIOB_26 3
#define PAD_ETH_RXM__PWM_14 4
#define PAD_ETH_RXM__CAM_VS0 5
#define PAD_ETH_RXM__SPI1_CS_X 6
#define PAD_ETH_RXM__IIS2_DI 7
#define VIVO_D10__PWM_1 0
#define VIVO_D10__VI1_D_10 1
#define VIVO_D10__VO_D_23 2
#define VIVO_D10__XGPIOB_11 3
#define VIVO_D10__RMII0_IRQ 4
#define VIVO_D10__CAM_MCLK0 5
#define VIVO_D10__IIC1_SDA 6
#define VIVO_D10__UART2_TX 7
#define VIVO_D9__PWM_2 0
#define VIVO_D9__VI1_D_9 1
#define VIVO_D9__VO_D_22 2
#define VIVO_D9__XGPIOB_12 3
#define VIVO_D9__CAM_MCLK1 5
#define VIVO_D9__IIC1_SCL 6
#define VIVO_D9__UART2_RX 7
#define VIVO_D8__PWM_3 0
#define VIVO_D8__VI1_D_8 1
#define VIVO_D8__VO_D_21 2
#define VIVO_D8__XGPIOB_13 3
#define VIVO_D8__RMII0_MDIO 4
#define VIVO_D8__SPI3_SDO 5
#define VIVO_D8__IIC2_SCL 6
#define VIVO_D8__CAM_VS0 7
#define VIVO_D7__VI2_D_7 0
#define VIVO_D7__VI1_D_7 1
#define VIVO_D7__VO_D_20 2
#define VIVO_D7__XGPIOB_14 3
#define VIVO_D7__RMII0_RXD1 4
#define VIVO_D7__SPI3_SDI 5
#define VIVO_D7__IIC2_SDA 6
#define VIVO_D7__CAM_HS0 7
#define VIVO_D6__VI2_D_6 0
#define VIVO_D6__VI1_D_6 1
#define VIVO_D6__VO_D_19 2
#define VIVO_D6__XGPIOB_15 3
#define VIVO_D6__RMII0_REFCLKI 4
#define VIVO_D6__SPI3_SCK 5
#define VIVO_D6__UART2_TX 6
#define VIVO_D6__CAM_VS0 7
#define VIVO_D5__VI2_D_5 0
#define VIVO_D5__VI1_D_5 1
#define VIVO_D5__VO_D_18 2
#define VIVO_D5__XGPIOB_16 3
#define VIVO_D5__RMII0_RXD0 4
#define VIVO_D5__SPI3_CS_X 5
#define VIVO_D5__UART2_RX 6
#define VIVO_D5__CAM_HS0 7
#define VIVO_D4__VI2_D_4 0
#define VIVO_D4__VI1_D_4 1
#define VIVO_D4__VO_D_17 2
#define VIVO_D4__XGPIOB_17 3
#define VIVO_D4__RMII0_MDC 4
#define VIVO_D4__IIC1_SDA 5
#define VIVO_D4__UART2_CTS 6
#define VIVO_D4__CAM_VS0 7
#define VIVO_D3__VI2_D_3 0
#define VIVO_D3__VI1_D_3 1
#define VIVO_D3__VO_D_16 2
#define VIVO_D3__XGPIOB_18 3
#define VIVO_D3__RMII0_TXD0 4
#define VIVO_D3__IIC1_SCL 5
#define VIVO_D3__UART2_RTS 6
#define VIVO_D3__CAM_HS0 7
#define VIVO_D2__VI2_D_2 0
#define VIVO_D2__VI1_D_2 1
#define VIVO_D2__VO_D_15 2
#define VIVO_D2__XGPIOB_19 3
#define VIVO_D2__RMII0_TXD1 4
#define VIVO_D2__CAM_MCLK1 5
#define VIVO_D2__PWM_2 6
#define VIVO_D2__UART2_TX 7
#define VIVO_D1__VI2_D_1 0
#define VIVO_D1__VI1_D_1 1
#define VIVO_D1__VO_D_14 2
#define VIVO_D1__XGPIOB_20 3
#define VIVO_D1__RMII0_RXDV 4
#define VIVO_D1__IIC3_SDA 5
#define VIVO_D1__PWM_3 6
#define VIVO_D1__IIC4_SCL 7
#define VIVO_D0__VI2_D_0 0
#define VIVO_D0__VI1_D_0 1
#define VIVO_D0__VO_D_13 2
#define VIVO_D0__XGPIOB_21 3
#define VIVO_D0__RMII0_TXCLK 4
#define VIVO_D0__IIC3_SCL 5
#define VIVO_D0__WG1_D0 6
#define VIVO_D0__IIC4_SDA 7
#define VIVO_CLK__VI2_CLK 0
#define VIVO_CLK__VI1_CLK 1
#define VIVO_CLK__VO_CLK1 2
#define VIVO_CLK__XGPIOB_22 3
#define VIVO_CLK__RMII0_TXEN 4
#define VIVO_CLK__CAM_MCLK0 5
#define VIVO_CLK__WG1_D1 6
#define VIVO_CLK__UART2_RX 7
#define PAD_MIPIRX5N__VI1_D_11 1
#define PAD_MIPIRX5N__VO_D_12 2
#define PAD_MIPIRX5N__XGPIOC_0 3
#define PAD_MIPIRX5N__CAM_MCLK0 5
#define PAD_MIPIRX5N__WG0_D0 6
#define PAD_MIPIRX5N__DBG_0 7
#define PAD_MIPIRX5P__VI1_D_12 1
#define PAD_MIPIRX5P__VO_D_11 2
#define PAD_MIPIRX5P__XGPIOC_1 3
#define PAD_MIPIRX5P__IIS1_MCLK 4
#define PAD_MIPIRX5P__CAM_MCLK1 5
#define PAD_MIPIRX5P__WG0_D1 6
#define PAD_MIPIRX5P__DBG_1 7
#define PAD_MIPIRX4N__CV_4WTDI_CR_SCL0 0
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__VI1_D_13 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__CV_4WTMS_CR_SDA0 0
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__VI1_D_14 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__CV_4WTDO_CR_2WTMS 0
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__VI1_D_15 2
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__CV_4WTCK_CR_2WTCK 0
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__VI1_D_16 2
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__VO_D_10 2
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__VI1_D_17 4
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__VO_D_9 2
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__VI1_D_18 4
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__VO_D_8 2
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__VO_D_7 2
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__VO_D_6 2
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__VO_D_5 2
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM4__VI0_D_15 0
#define PAD_MIPI_TXM4__SD1_CLK 1
#define PAD_MIPI_TXM4__VO_D_24 2
#define PAD_MIPI_TXM4__XGPIOC_18 3
#define PAD_MIPI_TXM4__CAM_MCLK1 4
#define PAD_MIPI_TXM4__PWM_12 5
#define PAD_MIPI_TXM4__IIC1_SDA 6
#define PAD_MIPI_TXM4__DBG_18 7
#define PAD_MIPI_TXP4__VI0_D_16 0
#define PAD_MIPI_TXP4__SD1_CMD 1
#define PAD_MIPI_TXP4__VO_D_25 2
#define PAD_MIPI_TXP4__XGPIOC_19 3
#define PAD_MIPI_TXP4__CAM_MCLK0 4
#define PAD_MIPI_TXP4__PWM_13 5
#define PAD_MIPI_TXP4__IIC1_SCL 6
#define PAD_MIPI_TXP4__DBG_19 7
#define PAD_MIPI_TXM3__VI0_D_17 0
#define PAD_MIPI_TXM3__SD1_D0 1
#define PAD_MIPI_TXM3__VO_D_26 2
#define PAD_MIPI_TXM3__XGPIOC_20 3
#define PAD_MIPI_TXM3__IIC2_SDA 4
#define PAD_MIPI_TXM3__PWM_14 5
#define PAD_MIPI_TXM3__IIC1_SDA 6
#define PAD_MIPI_TXM3__CAM_VS0 7
#define PAD_MIPI_TXP3__VI0_D_18 0
#define PAD_MIPI_TXP3__SD1_D1 1
#define PAD_MIPI_TXP3__VO_D_27 2
#define PAD_MIPI_TXP3__XGPIOC_21 3
#define PAD_MIPI_TXP3__IIC2_SCL 4
#define PAD_MIPI_TXP3__PWM_15 5
#define PAD_MIPI_TXP3__IIC1_SCL 6
#define PAD_MIPI_TXP3__CAM_HS0 7
#define PAD_MIPI_TXM2__CV_4WTMS_CR_SDA0 0
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__VO_D_0 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXM2__SD1_D2 7
#define PAD_MIPI_TXP2__CV_4WTDI_CR_SCL0 0
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__VO_CLK0 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__SD1_D3 7
#define PAD_MIPI_TXM1__CV_4WTDO_CR_2WTMS 0
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__VO_D_2 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__CV_4WTCK_CR_2WTCK 0
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__VO_D_1 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__VO_D_4 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__CAM_VS0 6
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__VO_D_3 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__CAM_HS0 6
#define PAD_MIPI_TXP0__DBG_13 7
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AINR_MIC__IIS2_DI 5
#define PAD_AUD_AINR_MIC__IIS1_DI 6
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTL__IIS2_LRCK 5
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#define PAD_AUD_AOUTR__IIS2_DO 5
#define PAD_AUD_AOUTR__IIS1_DO 6
#define GPIO_RTX__XGPIOB_23 3
#define GPIO_RTX__PWM_1 4
#define GPIO_RTX__CAM_MCLK0 5
#define GPIO_ZQ__PWR_GPIO_24 3
#define GPIO_ZQ__PWM_2 4

#endif /* __CV181X_PINLIST_SWCONFIG_H__ */
